Three-dimensional (3D) wafer-to-wafer, die-to-wafer or die-to-die vertical stack technology seeks to achieve the long-awaited goal of vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance. One major challenge of 3D interconnects on a single wafer or in a die-to-wafer vertical stack is through-silicon via (TSV) that provides a signal path for signals to traverse from one side of the wafer to the other. TSV is typically fabricated to provide the through-silicon via filled with a conducting material that passes completely through the layer to contact and connect with the other TSVs and conductors of the bonded layers.
In order to reduce the thickness of semiconductor packages, increase the chip speed, and for high-density fabrication, efforts to reduce the thickness of a semiconductor wafer are in progress. Thickness reduction is performed by so-called backside grinding of a semiconductor wafer on the surface opposite that containing pattern-formed circuitry, on which a temporary carrier is typically attached to support wafer handling through a glue layer during wafer thinning and subsequent processes. Currently, carrier technology faces tough challenge in bonding uniformity and high risk in de-bonding process while thickness of stacked wafer becoming thinner and thinner.
Polyimide (PI) has been widely used for stress buffer layer application on semiconductor devices because of its excellent thermal, mechanical and insulating properties as well as easy processing capabilities. As the PI layer is used at the final stage of the front-end process, compatibility with various organic and/or inorganic materials is important. In particular, PI adhesion has often been discussed in relation to device failure. For example, in some occasions, it fails to remove the glue layer from the PI layer in detaching the carrier from the wafer since the adhesion strength between the PI layer and the glue layer is strong, especially after thermal cycles. A conventional approach uses N2 plasma treatment to enhance adhesion between PI and underfill. Adversely, it increases the PI surface roughness and produces the covalent bond with the glue layer because of an amide or amine group generated on the PI layer.